ST7565V datasheet(65/72 Pages) SITRONIX

65 / 72 page

ST7565V

Ver 1.5b

65/72

2009/09/14

Table 28

(VDD = 2.7V, Ta = –30 to 85°C)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH6

—

Address setup time

tAW6

—

System cycle time

tCYC6

400

—

Enable L pulse width (WRITE)

tEWLW

220

—

Enable H pulse width (WRITE)

tEWHW

180

—

Enable L pulse width (READ)

tEWLR

220

—

Enable H pulse width (READ)

tEWHR

180

—

WRITE Data setup time

tDS6

—

WRITE Address hold time

tDH6

—

READ access time

tACC6

CL = 100 pF

—

140

READ Output disable time

D0 to D7

tOH6

CL = 100 pF

250

Table 29

(VDD = 1.8V, Ta = –30 to 85°C)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH6

—

Address setup time

tAW6

—

System cycle time

tCYC6

640

—

Enable L pulse width (WRITE)

tEWLW

360

—

Enable H pulse width (WRITE)

tEWHW

280

—

Enable L pulse width (READ)

tEWLR

360

—

Enable H pulse width (READ)

tEWHR

280

—

WRITE Data setup time

tDS6

—

WRITE Address hold time

tDH6

—

READ access time

tACC6

CL = 100 pF

—

240

READ Output disable time

D0 to D7

tOH6

CL = 100 pF

430

*1 The input signal rise time and fall time (

tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(

tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.

*2 All timing is specified using 20% and 80% of VDD as the reference.

tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

ST7565V Datasheet(PDF) 65 Page - Sitronix Technology Co., Ltd.

ST7565V Datasheet(HTML) 65 Page - Sitronix Technology Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL