ST8016 datasheet(8/28 Pages) SITRONIX

8 / 28 page

ST8016

Ver 2.0

Page 8/28

2008/05/07

to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H".

During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is

non-selected after 160 bits of data have been read.

OPTION_VDD

Option selection pin

For COG layout to reduce interface pins.

Normally let it open

Y1 -Y160

LCD drive output pins

Corresponding directly to each bit of the data latch, one level (V0, V12 or V43) is selected

and output.

Table of truth values is shown in "TRUTH TABLE" in Functional Operations.

(Common mode)

SYMBOL

FUNCTION

VDD

Logic system power supply pin, connected to +2.5 to +5.5 V.

VSS

Ground pin, connected to 0 V.

V0L, V0R

V12L, V12R

V43L, V43R

Bias power supply pins for LCD drive voltage

Normally use the bias voltages set by a resistor divider.

Ensure that voltages are set such that VSS < V43 < V12 < V0.

ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular

voltage that is assigned by specification for each power pin.

ElO1

Shift data input/output pin for bi-directional shift register

Output pin when L/R is at VSS level "L', input pin when L/R is at VDD level "H".

When L/R = H, ElO1 is used as input pin, it will be pulled down.

When L/R = L, ElO1 is used as output pin, it won't be pulled down.

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT

PINS" in Functional Operations.

EIO2

Shift data input/output pin for bi-directional shift register

Input pin when L/R is at VSS level "L", output pin when L/R is at VDD level "H".

When L/R = L, EIO2 is used as input pin, it will be pulled down.

When L/R = H, EIO2 is used as output pin, it won't be pulled down.

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT

PINS" in Functional Operations.

Shift clock pulse input pin for bi-directional shift register

* Data is shifted at the falling edge of the clock pulse.

L/R

Input pin for selecting the shift direction of bi-directional shift register

Data is shifted from Y160 to Y1 when set to VSS level "L", and data is shifted from Y1 to Y160

when set to VDD level "H".

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT

PINS" in Functional Operations.

/DISPOFF

Control input pin for output of non-select level

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and

controls the LCD drive circuit.

When set to VSS level "L", the LCD drive output pins (Y1-Y160) are set to level Vss.

When set to "L”, the contents of the shift register are reset to not reading data. When the

/DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift

data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does

not correspond to what is shown in AC characteristics, the shift data is not read correctly.

Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

AC signal input pin for LCD drive waveform

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and

controls the LCD drive circuit.

Normally it inputs a frame inversion signal.

The LCD drive output pins' output voltage levels can be set using the shift register output

signal and the FR signal.

Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

Mode selection pin

When set to VSS level "L", single mode operation is selected; when set to VDD level "H" dual

mode operation is selected.

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT

PINS" in Functional Operations.

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