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ENC424J600 Datasheet(PDF) 84 Page - Microchip Technology

Part # ENC424J600
Description  Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
PDF  168 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ENC424J600 Datasheet(HTML) 84 Page - Microchip Technology

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ENC424J600/624J600
DS39935C-page 82
 2010 Microchip Technology Inc.
REGISTER 8-5:
MAIPG: MAC INTER-PACKET GAP REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
—
r
r
r
r
r
r
r
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
—
IPG6
IPG5
IPG4
IPG3
IPG2
IPG1
IPG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented:
Read as ‘0’
bit 14-8
Reserved:
Write as ‘0001100’ (0Ch)
bit 7
Unimplemented:
Read as ‘0’
bit 6-0
IPG<6:0>:
Non Back-to-Back Inter-Packet Gap Delay Time Control bits
Inter-Packet Gap (IPG) between the end of one packet received or transmitted and the start of the next
packet transmitted. For maximum performance while meeting IEEE 802.3 compliance, leave this field
set to 12h, which represents an Inter-Packet Gap time of 0.96
s (at 100 Mb/s) or 9.6 s (at 10 Mb/s).
REGISTER 8-6:
MACLCON: MAC COLISION CONTROL REGISTER
U-0
U-0
R/W-1
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
—
—
r
r
r
r
r
r
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
MAXRET3
MAXRET2
MAXRET1
MAXRET0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented:
Read as ‘0’
bit 13-8
Reserved:
Write as ‘110111’ (37h)
bit 7-4
Unimplemented:
Read as ‘0’
bit 3-0
MAXRET<3:0>:
Maximum Retransmissions Control bits (half duplex only)
Maximum retransmission attempts the MAC will make before aborting a packet due to excessive
collisions.



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