ENC424J600 datasheet(89/168 Pages) MICROCHIP

89 / 168 page

 2010 Microchip Technology Inc.

DS39935C-page 87

ENC424J600/624J600

It is possible for the host application to write to the

receive buffer. However, it is recommended not to do

so outside of the area protected by the Tail Pointer in

order to prevent it from being subsequently overwritten

by future receive packets.

ERXHEAD is a read-only register and may be updated

at any time by hardware. The high byte is shadowed to

ensure it can be safely read on 8-bit interfaces (SPI or

PSP). When reading ERXHEAD, read the low byte first.

This operation simultaneously copies the high byte to a

shadow register. Reading the high byte automatically

reads from this shadow register. This ensures that the

value has not been modified since the low byte was

obtained, even if another packet has been received in

the interim.

9.2.1

CONFIGURING PACKET

RECEPTION

Once the MAC and PHY are properly initialized, the

device is ready to begin receiving packets.

To enable reception:

Program the ERXST Pointer (low byte first if

writing a byte at a time) to the first address to be

used for the receive buffer. This pointer must

indicate an even address. The Head Pointer,

ERXHEAD, will automatically be set to the same

value.

In the host controller application, create a

variable, NextPacketPointer, to hold the

address value of the next received packet.

Initialize this variable to be equal to the current

value of ERXST.

Program the Tail Pointer, ERXTAIL, to the last

even address of the buffer or 5FFEh.

Configure

interrupts

desired.

See

Section 13.0 “Interrupts”

for more information.

Set RXEN (ECON1<0>) to enable reception.

Once RXEN is set, it is recommended that ERXST not

be modified. The host controller must monitor the

ENCX24J600 to determine when a packet has arrived

and is ready to be processed. This is accomplished by

using the packet pending interrupt as described in

Section 13.1.5

“Received

Packet

Pending”

Alternatively, poll the PKTCNT bits for a non-zero

value.

9.2.2

STORAGE OF INCOMING PACKETS

Packets are stored sequentially in the receive buffer.

Each frame is stored as it was presented to the MAC,

including all padding and frame check (CRC) bytes, but

excluding any preamble or start of stream/frame delim-

iter bytes. Frames are always saved starting on an

even address, so those with an odd length skip one

byte before the next frame begins. A sample packet

stored in memory is shown in Figure 9-4.

When a packet is received, the hardware increments

the Packet Counter bits, PKTCNT (ESTAT<7:0>).

Incoming bytes are written sequentially, beginning at

the Head Pointer, ERXHEAD. If the Head Pointer

reaches the Tail Pointer, ERXTAIL, during reception, or

if incrementing the PKTCNT bits would cause an over-

flow, the packet will be discarded and the Head Pointer

restored.

Each received frame is preceded in memory by a

pointer to the next frame and a Receive Status Vector

(RSV). The RSV includes the length of the frame, and

flags indicating the type of packet and which filters

were matched. This format of the RSV is shown in

Table 9-1.

To retrieve a packet from the buffer:

Verify that a packet is waiting by ensuring that

the PKTCNT<7:0> bits are non-zero or that

PKTIF (EIR<6>) is set.

Begin reading at address pointed to by the

application

variable,

NextPacketPointer

(see

Section 9.2.1

“Configuring

Packet

Reception”

Read the first two bytes of the packet, which are

the address of the next packet and write to

NextPacketPointer

Read the next six bytes, which are the Receive

Status Vector (RSV).

Read the Ethernet frame. The number of bytes

to be read is indicated by the received byte

count in the RSV read during step 4.

As the frame is read and processed, incremental

amounts of memory buffer can be freed up by

updating the ERXTAIL Pointer value to the point

where the packet has been processed, taking

care to wrap back at the end of the received

memory buffer. Once the whole frame has been

processed, the final value of ERXTAIL should be

equal to (NextPacketPointer – 2).

Set PKTDEC (ECON1<8>) to decrement the

PKTCNT bits. PKTDEC is automatically cleared

by hardware if PKTCNT decrements to zero.

ENC424J600 Datasheet(PDF) 89 Page - Microchip Technology

ENC424J600 Datasheet(HTML) 89 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL