ENC424J600 datasheet(11/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 9

ENC424J600/624J600

2.0

EXTERNAL CONNECTIONS

2.1

Oscillator

ENC424J600/624J600 devices are designed to

operate from a fixed 25 MHz clock input. This clock can

be generated by an external CMOS clock oscillator or

a parallel resonant, fundamental mode 25 MHz crystal

attached to the OSC1 and OSC2 pins. Use of a crystal,

rated for series resonant operation, will oscillate at an

incorrect frequency. To comply with IEEE 802.3 Ethernet

timing requirements, the clock must have no more than

±50 ppm of total error; avoid using resonators or clock

generators that exceed this margin.

When clocking the device using a crystal, follow the

connections shown in Figure 2-1. When using a CMOS

clock oscillator or other external clock source, follow

Figure 2-2.

FIGURE 2-1:

CRYSTAL OSCILLATOR

OPERATION

FIGURE 2-2:

EXTERNAL CLOCK

SOURCE

2.2

CLKOUT Pin

The Clock Out pin (CLKOUT) is provided for use as the

host controller clock or as a clock source for other

devices in the system. Its use is optional.

The 25 MHz clock applied to OSC1 is multiplied by a

PLL to internally generate a 100 MHz base clock. This

100 MHz clock is driven through a configurable

postscaler to yield a wide range of different CLKOUT

frequencies. The PLL multiplication adds clock jitter,

subject to the PLL jitter specification in Section 17.0

“Electrical Characteristics”. However, the postscaler

ensures that the clock will have a nearly ideal duty

cycle.

The CLKOUT function is enabled and the postscaler is

selected via the COCON<3:0> bits (ECON2<11:8>).

To create a clean clock signal, the CLKOUT output and

COCON bits are unaffected by all resets and

power-down modes. The CLKOUT function is enabled

out of POR and defaults to producing a 4 MHz clock.

This allows the device to directly clock the host

processor.

When the COCON bits are written with a new

configuration, the CLKOUT output transitions to the

new frequency without producing any glitches. No high

or low pulses with a shorter period than the original or

new clock are generated.

C1(3)

C2(3)

XTAL

OSC2

RS(1)

OSC1

RF(2)

To Internal Logic

Note 1: A series resistor, RS, may be required for

crystals with a low drive strength specification

or when using large loading capacitors.

2: The feedback resistor, RF , is typically 1.5 M



approx.

3: The load capacitors’ value should be derived

from the capacitive loading specification

provided by the crystal manufacture.

ENCX24J600

3.3V Clock from

External System(1)

OSC1

OSC2

Open

Note 1: Duty cycle restrictions must be observed.

ENCX24J600

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