DM9102DEP datasheet(50/70 Pages) DAVICOM

50 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

7.4 Serial Management Interface

The serial management interface is used to obtain and

control the status of PHY management register set through

the internal MDC and MDIO signals, which is control by

CR9 bits 19:16. The Management Data Clock (MDC) is

equipped with a maximum clock rate of 2.5MHz.

In read/write operation, the management data frame is

64-bit long start with 32 contiguous logic one bits (preamble)

synchronization clock cycles on MDC. The Start of Frame

Delimiter (SFD) is indicated by a <01> pattern followed by

the operation code (OP):<10> indicates Read operation and

<01> indicates Write operation. Following the OP Code is

the 5-bit PHY Address field that is fixed to 00001b. For read

operation, a 2-bit turnaround (TA) filing between Register

Address field and Data field is provided for MDIO to avoid

contention. “Z” stands for the state of high impedance.

Following turnaround time, a 16-bit data is read from or

written onto management registers.

7.4.1 Management Interface - Read Frame Structure

32 "1"s

Idle

Preamble

SFD

Op Code

PHY Address

Turn Around

Data

Idle

Read

Write

MDC

MDIO Read

D15

D14

7.4.2 Management Interface - Write Frame Structure

32 "1"s

D15

D14

Idle

Preamble

SFD

Op Code

PHY Address

Turn Around

Data

Idle

Write

MDC

MDIO Write

DM9102DEP Datasheet(PDF) 50 Page - Davicom Semiconductor, Inc.

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