TLC5970RHPR datasheet(12/48 Pages) TI

12 / 48 page

TLC5970

SBVS140 – MARCH 2010

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

NAME

DAP

RHP

I/O

DESCRIPTION

SDTA

Noninverting serial data input

SDTB

Inverting serial data input

Noninverting data shift clock input. All data in the Common Shift Register are shifted to the

MSB side by 1 bit and synchronized to the rising edge of the differential clock generated by

SCKA

SCKA and SCKB. The differential data made by SDTA and SDTB are shifted into the

Common Shift Register LSB at the same time.

Inverting data shift clock input. All data in the shift register are shifted to the MSB side by 1 bit

synchronized to the rising edge of the differential clock generated by SCKA and SCKB. The

SCKB

differential data made by SDTA and SDTB are shifted into the Common Shift Register LSB at

the same time.

SDTY

Noninverting serial data output

SDTZ

Inverting serial data output

SCKY

Noninverting serial data shift clock output

SCKZ

Inverting serial data shift clock output

Disable buck converter. When SWOFF is connected to VREG, the buck converter is not

operated and the OVP/SCP flag is not set even if the device is in an error condition. When

SWOFF

SWOFF is low, the buck converter is operated. This terminal is internally pulled down to GND

by approximately a 10 k

Ω resistor.

EEPROM writing power supply. When this pin level is 19 V, EEPROM can be programmed for

VROM

dot correction data. This pin must be open in normal operation. This terminal is pulled down to

GND by approximately a 10 k

Ω resistor internally.

IREF0

I/O

The resistors connected from IREF0, IREF1, and IREF2 to GND set the maximum sink current

IREF1

I/O

for OUT0, OUT1, and OUT2, respectively.

IREF2

I/O

OUT0

Constant-current sink output. Multiple outputs can be tied together to increase the

OUT1

constant-current capability.

OUT2

Internal regulator output. This pin requires a 0.01 µF decoupling capacitor to ground. This

VREG

output cannot be used for any other function and no current can be pulled from this output.

Internal regulator output for the differential interface circuit. This pin requires a 0.1 µF

VREGIF

decoupling capacitor. This output cannot be used for any other function and no current can be

pulled from this output.

Feedback voltage input for the converter and power-supply for differential signal interface

output and LED driver. Connect this pin to the dc/dc converter output voltage. The FB pin

must not be opened, otherwise higher voltage than the absolute maximum voltage is

generated.

Source of the high-side power MOSFET. Connected to an external inductor and diode.

Boost capacitor for the high-side power MOSFET gate driver. A capacitor is connected

BOOT

I/O

between BOOT and PH.

VCC

—

Power-supply voltage

GND

—

Power ground

5, 9, 11, 14,

No internal connection. These pins are not electrically connected to the IC. They should be

8, 11, 14,

19, 22, 26,

soldered to the PCB. Connecting these pins to ground provides improved thermal

23, 25

28, 31

performance.

The DAP package thermal pad is electrically connected to ground inside the package. This

pad should be connected to the ground plane on the PCB for best thermal performance. It

does not need to be soldered to the PCB if thermal performance is not needed. This pad

cannot be connected to any other voltage other than ground. See the mechanical drawings at

Thermal

the end of this document for more information.

—

pad

The RHP package thermal pad is electrically connected to ground inside the package. This

pad must be connected to the ground plane on the PCB for best thermal performance and for

mechanical reasons. This pad cannot be connected to any other voltage other than ground.

See the mechanical drawings at the end of this document for more information.

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