NJU8758 datasheet(8/8 Pages) NJRC

8 / 8 page

NJU8758

- 8 -

Ver.2009-11-10

TYPICAL APPLICATION CIRCUIT

Note 8) De-coupling capacitors must be connected between each power supply terminal and GND (VDD-VSS,

VDDO-VSS).

Note 9) VSS should be connected at a nearest point to the IC on PCB.

Note 10) IN, EQ1 and EQ2 should be not designed near OUTP and OUTN, which emit PWM noise.

Note 11) The power supply for VDDO requires fast driving response performance such as a switching regulator

for better THD.

Note 12) The above circuit shows only application example and does not guarantee the any electrical

characteristics. Therefore, please test the circuit carefully to fit your application.

Note 13) The transition time for MUTEB and STBYB signals must be less than 100

µs. Otherwise, a

malfunction may be occurred.

Note 14) (1) – (12) indicates terminal number.

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

OUTP(12)

OUTN(10)

COM(5)

10 µF

8 Ω

VDD(1)

VSS(9,13)

VDDO(11)

IN(2)

STBYb(7)

MUTEb(6)

1 µF

TEST(8)

0.1 µF

10 µF

1 µF

10 µF

Battery

EQ1(3)

EQ2(4)

100 pF

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