WM8144 datasheet(10/27 Pages) WOLFSON

10 / 27 page

WM8144-10

Wolfson Microelectronics

S/H, Offset DAC’s and PGA

Each analogue input (RINP, GINP, BINP) of the WM8144-

10 consists of a sample and hold, a programmable gain

amplifier, and a DC offset correction block. The operation

of the red input stage is summarised in Figure 1.

S/H

Gain=G

VMID

VADC

VMID

Voffset

RINP

Figure 1

The sample/hold block can operate in two modes of op-

eration, CDS (Correlated Double Sampling) or Single Ended.

In CDS operation the video signal processed is the differ-

ence between the voltage applied at the RINP input when

RS occurs, and the voltage at the RINP input when VS

occurs. This is summarised in Figure 2.

Vrs

Vvs

Figure 2

When using CDS the actual DC value of the input signal is

not important, as long as the signal extremes are main-

tained within 0.5 volts of the chip power supplies. This is

because the signal processed is the difference between

the two sample voltages, with the common DC voltage

being rejected.

In single ended operation, the VS and RS control signals

occur simultaneously, and the voltage applied to the re-

set switch is fixed at VMID. This means that the voltage

processed is the difference between the voltage applied

to RINP when VS/RS occurs, and VMID. When using Sin-

gle ended operation the DC content of the video signal is

not rejected.

The Programmable Gain Amplifier block multiplies the re-

sulting input voltage by a value between 0.5 and 8.25

which can be programmed independently for each of the

three input channels via the serial (or parallel) interface.

PGA gain is dependent on the 5-bit binary code pro-

grammed in the PGA registers. A typical plot of PGA

gain versus code is shown on Page 8. The DC value of

the gained signal can then be trimmed by the 8 bit plus

sign DAC. The voltage output by this DAC is shown as

Voffset in Figure 1. The range of the DAC is (VMID/2).

The output from the offset DAC stage is referenced to

the VMID voltage. This allows the input to the ADC to

maximise the dynamic range, and is shown diagrammati-

cally in Figure 1 by the final VMID addition.

For the input stage the final analogue voltage applied to

the ADC can be expressed as:

Where: VADC is the voltage applied to the ADC

G is the programmed gain

Vvs is the voltage of the video sample

Vrs is the voltage of the reset sample

Sign is the Offset DAC sign bit

DAC_CODE is the offset DAC value

VMID is the WM8144-10 generated VMID voltage

The ADC has a lower reference of VRB (typically 1.5 V)

and an upper reference of VRT (typically 3.5 V). When

an ADC input voltage is applied to the ADC equal to VRB

the resulting code is 000(hex). When an ADC input volt-

age is applied to the ADC equal to VRT the resulting code

is 3FF(hex).

Reset Level Clamp

Both CDS and Single ended operation can be used with

Reset Level Clamping. A typical input configuration is

shown in Figure 3.

S/H

Gain=G

VMID

VRLC

RINP

Cin

WM8144

Figure 3

Theory of Operation

()

VADC

G Vvs Vrs

1 2 * Sign *

DAC_ CODE

255

=−

−









VMID

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