WM8706

Product Preview

WOLFSON MICROELECTRONICS LTD

PP Rev 1.2 April 2001

12

AUDIO DATA SAMPLING RATES

The master clock for WM8706 supports audio sampling rates from 128fs to 768fs, where fs is

the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The

master clock is used to operate the digital filters and the noise shaping circuits.

The WM8706 has a master clock detection circuit that automatically determines the relation

between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If

there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.

The master clock should be synchronised with LRCIN, although the WM8706 is tolerant of

phase differences or jitter on this clock.

MASTER CLOCK FREQUENCY (MHZ) (XTI)

SAMPLING

RATE

(LRCIN)

128fs

192fs

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.114

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

Unavailable

192kHz

24.576

36.864

Unavailable

Unavailable

Unavailable

Unavailable

Table 1 Typical Relationships Between System Frequency and Sampling Rates.

HARDWARE CONTROL MODES

When the MODE pin is held low, the following hardware modes of operation are available.

MUTE AND AUTOMUTE OPERATION

In both hardware and software modes, pin 25 (MUTEB) controls selection of MUTE directly, and

can be used to enable and disable the automute function, or as an output of the automuted signal.

MUTEB PIN

DESCRIPTION

0

Mute DAC channels

1

Normal Operation

Floating

Enable IZD, MUTEB becomes an output to indicate when IZD occurs.

Table 2 Mute and Automute Control

Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being

played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)

begins to decay exponentially from the DC level of the last input sample. The output will decay

asserted, the output will restart almost immediately from the current input sample.