X88C75PI datasheet(9/27 Pages) XICOR

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X88C75 SLIC® E2

Interrupt Status Register (ISR)

The Interrupt Status Register is a volatile register used

to configure the interrupt condition for the I/O ports as

well as to determine the interrupt status of the ports. The

X88C75 ports can generate an interrupt to the microcon-

troller upon the proper transition (as specified in the

configuration register) on either STRA or STRB pins

when the corresponding I/O port is configured as an

input.

The INT flag is set when any of the input strobes are

toggled provided that their corresponding interrupt en-

able bits (ENA, ENB) are set. The INT flag is cleared

when latched data is read (PDR) or pending interrupt

status flag (INTA, INTB) in ISR is forced to “0” by the

interrupt service routine. Interrupt service routine should

examine the interrupt status flags (INTA, INTB) and

identify the source of pending interrupt.

The E2 memory interrupt status flag (EOW) is another

means to detect the early completion of a write cycle.

When ENEE is enabled, the hardware will set the EOW

flag, and interrupt the microcontroller at the end of an

internal programming cycle. Toggle Bit Polling can be

replaced by this hardware interrupt, which reduces the

software overhead. The EOW flag should be cleared by

software. The interrupt status register bits are mapped

as follows.

Figure 10. Interrupt Status Register

INT

2887 ILL F14.1

INTA INTB

ENA

ENB ENEE

EOW

76543210

Interrupt Flag

“0” = No pending interrupt

“1” = Interrupt request

Port B – Interrupt Status

“0” = No pending interrupt

“1” = Port B latched data when a valid

transition occurred on the STRB

and port B was an input port.

Port A – Interrupt Enable

“0” = Mask off interrupt

“1” = Interrupt enabled

Port B – Interrupt Enable

“0” = Mask off interrupt

“1” = Interrupt enabled

EEPROM Interrupt Enable

“0” = Mask off interrupt

“1” = Interrupt enabled

EEPROM Interrupt Status

“0” = Programming in progress

“1” = Set by hardware when it completes

programming the previously

written data

Port A – Interrupt Status

“0” = No pending interrupt

“1” = Port A latched data when a valid

transition occurred on the STRA

and port A was an input port.

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