X88C75PI datasheet(6/27 Pages) XICOR

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X88C75 SLIC® E2

that accessing the BPR automatically sets the upper

level SDP. If for some reason the user does not want

SDP enabled, they may reset it using the normal reset

command sequence. This will not affect the state of the

BPR and any 1K x 8 blocks that were set to the write

lockout state will remain in the write lockout state.

Figure 4. Block Protect Register Format

Figure 5. Setting BPR Command Sequence

The BPR format and block map are illustrated above.

The command sequence is illustrated to the right.

MSB

LSB

BLOCK

ADDRESS

0000-03FF

0400-07FF

0800-0BFF

0C00-0FFF

1000-13FF

1400-17FF

1800-1BFF

1C00-1FFF

“1” = Protect, “0” = Unprotect Block Specified

2887 ILL F08.1

P 555

b1 b0

AAA

b1 b0

P 555

b1 b0

P 555

b1 b0

2887 ILL F09.1

b1 b0

Write BPR mask value

to any address

Reference the A15–A13

setting in E2M register

Delay of tWC

Exit Routine

(BPR Register Set Global SDP Set)

b2 b1 b0

P = Address bit (A12) of the

memory plane not being read.

Figure 6. Microcontroller Map

0000

1FFF

FFFF

2887 ILL F29.1

RESET/ISR VECTORS

USER

APPLICATION

CODE/DATA

8K BYTES OF BYTE

ALTERABLE DUAL

PLANE ARCHITECTURED

NON-VOLATILE MEMORY

(MAPPABLE TO ANY 8K

PAGE BY THE E2M BITS 2–0)

SRF (SPECIAL FUNCTION

(MAPPABLE TO ANY 1K

PAGE BY THE SFRM

0030

0150

0000

1F00

1FFF

FC00

FFFF

SLIC

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