X88C75PI datasheet(7/27 Pages) XICOR

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X88C75 SLIC® E2

Figure 7. On-Chip Registers

Programmable Address Decoding

The X88C75 features an internal programmable ad-

dress decoder which allows the nonvolatile memory

array and the internal registers to be mapped in various

locations of the 64K-byte memory map. The register set

is mappable into a 1K-byte block, while the nonvolatile

memory array is mappable into an 8K-byte block. The

mapping is controlled by two nonvolatile configuration

registers, the SFR Map Register and the E2 Memory

Map Register. Their bits are mapped as follows:

SFR Map Register (SFRM)

Default = 3F

A15

A14

A13

A12

A11

A10

2887 ILL F10

543

A15-A10

The A15-A10 are upper address bits for the 1K-byte

page where the SFR memory is mapped.

2887 ILL F30.2

LAM

RST

A15

A14

A13

76543210

FC38

EEM*

E2 Memory Map Register

MSB

LSB

FC08

PDRB

Port Data Register B

MSB

LSB

FC10

PDRA

Port Data Register A

INT

INTA INTB

ENA

ENB ENEE

EOW

FC18

ISR

Interrupt Status Register

IRST

AWO BWO DIRA DIRB STRA STRB

FC20

Configuration Register

MSB

LSB

FC28

PPRB

Port Pin Register B

MSB

LSB

FC30

PPRA

Port Pin Register A

Special Function Register

Memory Map Register

NOTE: * The value returned by reading these registers is the complement of the

actual data. These registers are nonvolatile and a special SDP sequence

is used to alter their contents. All the other registers are initialized by a

valid reset input signal and when the device is power cycled.

A15

A14

A13

A12

A11

A10

FC00

SFRM*

FE00

FE0F

16 Bytes General Purpose SRAM

MSB

LSB

MSB

LSB

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