17

Note: (5)

This parameter is periodically sampled and not 100% tested.

PSEN Controlled Read Timing Diagram

PSEN Controlled Read Cycle

Symbol

Parameter

Min.

Max.

Units

ALE Pulse Width

80

ns

Address Setup Time

20

ns

Address Hold Time

30

ns

PSEN Read Access Time

120

ns

Data Hold Time

0

ns

Chip Enable Setup Time

7

ns

PSEN Pulse Width

150

ns

PSEN Setup Time

30

ns

PSEN Hold Time

20

ns

PSEN Disable to Output in High Z

50

ns

PSEN to Output in Low Z

10

ns

2887 PGM T10

EQUIVALENT A.C. TEST CIRCUIT

A.C. CONDITIONS OF TEST

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

10ns

Input and Output Timing Levels

1.5V

2887 PGM T09.1

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ALE

A/D0–A/D7

A8–A12

PSEN

AIN

tPLDV

DOUT

2887 ILL F23

tPH

tPH

tLHLL

tAVLL

tLLAX

tPS

PWPL

ADDRESS

CE

tPLDX

tPHDZ

tPHDX

tELLL

2887 ILL F22.2

5V

1.92K

Ω

100pF

OUTPUT

1.37K

Ω