AM1707 datasheet(188/198 Pages) TI

188 / 198 page

AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

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6.32 IEEE 1149.1 JTAG

The JTAG(1) interface is used for BSDL testing and emulation of the device.

The device requires that both TRST and RESET be asserted upon power up to be properly initialized.

While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required

for proper operation.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for

the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG

port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or

exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by

TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE

correctly. Other boundary-scan instructions work correctly independent of current state of RESET.

For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that

TRST will always be asserted upon power up and the device's internal emulation logic will always be

properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG

controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary scan operations.

6.32.1

JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)

Table 6-113. DEVIDR0 Register

BYTE ADDRESS

ACRONYM

COMMENTS

0x01C1 4018

DEVIDR0

JTAG Identification Register

Read-only. Provides 32-bit JTAG ID of the device.

(1)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each

silicon revision is:

•

0x8B7D F02F for silicon revision 1.1

•

0x9B7D F02F for silicon revision 2.0

For the actual register bit names and their associated bit field descriptions, see Figure 6-73 and

Table 6-114.

31-28

27-12

11-1

VARIANT (4-Bit)

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

R-xxxx

R-1011 0111 1101 1111

R-0000 0010 111

R-1

LEGEND: R = Read, W = Write, n = value at reset

Figure 6-73. JTAG ID (DEVIDR0) Register Description - Register Value

188

Peripheral Information and Electrical Specifications

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