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AM1707 Datasheet(PDF) 189 Page - Texas Instruments |
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AM1707 Datasheet(HTML) 189 Page - Texas Instruments |
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189 / 198 page ![]() TCK TDO 1 7 2 3 RTCK 4 5 6 9 8 TDI/TMS/TRST AM1707 www.ti.com SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010 Table 6-114. JTAG ID Register Selection Bit Descriptions BIT NAME DESCRIPTION 31:28 VARIANT Variant (4-Bit) value 27:12 PART NUMBER Part Number (16-Bit) value 11-1 MANUFACTURER Manufacturer (11-Bit) value 0 LSB LSB. This bit is read as a "1". 6.32.2 JTAG Test-Port Electrical Data/Timing Table 6-115. Timing Requirements for JTAG Test Port (see Figure 6-74) No. PARAMETER MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 40 ns 2 tw(TCKH) Pulse duration, TCK high 16 ns 3 tw(TCKL) Pulse duration, TCK low 16 ns 4 tc(RTCK) Cycle time, RTCK 40 ns 5 tw(RTCKH) Pulse duration, RTCK high 16 ns 6 tw(RTCKL) Pulse duration, RTCK low 16 ns 7 tsu(TDIV-RTCKH) Setup time, TDI/TMS/TRST valid before RTCK high 4 ns 8 th(RTCKH-TDIV) Hold time, TDI/TMS/TRST valid after RTCK high 4 ns Table 6-116. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 6-74) No. PARAMETER MIN MAX UNIT 9 td(RTCKL-TDOV) Delay time, RTCK low to TDO valid 15 ns Figure 6-74. JTAG Test-Port Timing Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 189 Submit Documentation Feedback Product Folder Link(s): AM1707 |
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