GTL2007_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 16 February 2007

3 of 20

NXP Semiconductors

GTL2007

12-bit GTL to LVTTL translator with power good control

5.

Functional diagram

(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and

the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.

Fig 1.

Logic diagram of GTL2007

002aab210

GTL2007

1BI

2BI

27

26

GTL inputs

7BO1

25

7BO2

24

GTL outputs

EN2

23

LVTTL input

11BO

22

GTL output

5BI

6BI

21

20

3BI

19

4BI

18

GTL inputs

7

11BI

8

11A

9

9BI

LVTTL input/output

(open-drain)

GTL input

GTL input

1

VREF

2

1AO

3

2AO

4

5A

5

6A

6

EN1

LVTTL input

GTL

LVTTL inputs/outputs

(open-drain)

LVTTL outputs

10

3AO

11

4AO

LVTTL outputs

10BO1

17

10BO2

16

GTL outputs

12

10AI1

13

10AI2

LVTTL inputs

9AO

15

LVTTL output

1

1

1

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