DRV8800RTYR datasheet(13/26 Pages) TI

13 / 26 page

DRV8800

DRV8801

www.ti.com

SLVS855D – JULY 2008 – REVISED APRIL 2010

Control Logic Table(1)

PINS

OPERATION

PHASE

ENABLE

MODE 1

MODE 2

nSLEEP

OUT+

OUT-

Forward

Reverse

Brake (slow decay)

Fast-decay synchronous

rectification(2)

Fast-decay synchronous

rectification(2)

Sleep mode

(1)

X = Don’t care, Z = high impedance

(2)

To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current

approaches 0 A.

Overcurrent Protection

The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not

shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven

low, and a 1.2-ms fault timer is started. After this 1.2-ms period, tOCP , the device is then allowed to follow the

input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is

still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present,

normal operation resumes and nFAULT is deasserted.

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DRV8800RTYR Datasheet(PDF) 13 Page - Texas Instruments