P =I (2

R

)

D

DS(on)Sink

2

´

DRV8800

DRV8801

SLVS855D – JULY 2008 – REVISED APRIL 2010

www.ti.com

Slow-Decay SR (Brake Mode)

In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-bridge’s

low side (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers:

(2)

SENSE

A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To

minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an

independent ground return to the star ground point. This trace should be as short as possible. For low-value

sense resistors, the IR drops in the PCB can be significant, and should be taken into account.

NOTE

When selecting a value for the sense resistor, SENSE does not exceed the maximum

voltage of ±500 mV. The H-bridge is disabled and enters recirculation while motor winding

current is above a SENSE voltage equal or greater than 500 mV.

Ground

A ground power plane should be located as close to the DRV8800/DRV8801 as possible. The copper ground

plane directly under the PowerPAD package makes a good location. This pad can then be connected to ground

for this purpose.

Layout

The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal

performance, the DRV8800/DRV8801 must be soldered directly onto the board. On the underside of the

DRV8800/DRV8801 is a PowerPAD package, which provides a path for enhanced thermal dissipation. The

thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer

heat to other layers of the PCB. For more information on this technique, please refer to document SLMA002.

The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 mF) in parallel with a

ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB,

connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in

order to minimize lead inductance.

Pack Material Information

Table 1. Pin 1 Quadrants

Reel

Reel

Package

Package

Width

A0

B0

K0

P1

W

Pin1

Device

Pins

SPQ

Diameter

Type

Drawing

W1

(mm)

(mm)

(mm)

(mm)

(mm)

Quadrant

(mm)

(mm)

DRV8800PWPR

HTSSOP

PWP

16

2000

330

12.4

6.9

5.6

1.6

8

12

Q1

DRV8800RTYR

QFN

RTY

16

3000

330

12.4

4.25

4.25

1.15

8

12

Q2

DRV8800RTYT

QFN

RTY

16

250

180

12.4

4.25

4.25

1.15

8

12

Q2

DRV8800PWPR

HTSSOP

PWP

16

2000

330

12.4

6.9

5.6

1.6

8

12

Q1

DRV8800RTYR

QFN

RTY

16

3000

330

12.4

4.25

4.25

1.15

8

12

Q2

DRV8800RTYT

QFN

RTY

16

250

180

12.4

4.25

4.25

1.15

8

12

Q2

16

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