PCA9530_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 26 February 2009

7 of 24

NXP Semiconductors

PCA9530

6.6 External RESET

RESET input is once again HIGH.

7.

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 6).

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 7).

Fig 6.

Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 7.

Definition of START and STOP conditions

mba608

SDA

SCL

P

STOP condition

S

START condition