PCF8566P datasheet(33/48 Pages) NXP

33 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

33 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display conﬁgurations of up to sixteen PCF8566s can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I2C-bus slave address (SA0).

Cascaded PCF8566s are synchronized. They can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8566s of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 26).

Table 21.

Addressing cascaded PCF8566

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

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