PCF8566P datasheet(16/48 Pages) NXP

16 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

16 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

The lower clock frequency has the disadvantage of increasing the response time when

large amounts of display data are transmitted on the I2C-bus. When a device is unable to

process a display data byte before the next one arrives, it holds the SCL line LOW until the

ﬁrst display data byte is stored. This slows down the transmission rate of the I2C-bus but

no data loss occurs.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs and one column of the display RAM.

7.8 Shift register

The shift register transfers display information from the display RAM to the display register

while previous data is displayed.

7.9 Segment outputs

The LCD drive section includes 24 segment outputs S0 to S23 which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data resident in the display register. When less than

24 segment outputs are required, the unused segment outputs should be left open-circuit.

7.10 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left as an

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.11 Display RAM

The display RAM is a static 24

× 4-bit RAM which stores LCD data. Logic 1 in the RAM bit

map indicates the on-state of the corresponding LCD segment; similarly, logic 0 indicates

the off-state. There is a direct relationship between the RAM addresses and the segment

outputs, and between the individual bits of a RAM word and the backplane outputs. The

ﬁrst RAM row corresponds to the 24 segments operated with respect to backplane BP0

(see Figure 10). In multiplexed LCD applications, the segment data of rows 1 to 4 of the

display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

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