TAS5615 datasheet(10/34 Pages) TI

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TAS5615

SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010

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AUDIO SPECIFICATION (PBTL)

PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,

GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM = 15 mH, CDEM = 680 nF, MODE =

101-BD, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RL = 4 Ω, 10% THD+N, clipped output signal

300

RL = 6 Ω, 10% THD+N, clipped output signal

210

RL = 8 Ω, 10% THD+N, clipped output signal

160

Power output per channel

RL = 4 Ω, 1% THD+N, unclipped output signal

240

RL = 6 Ω, 1% THD+N, unclipped output signal

160

RL = 8 Ω, 1% THD+N, unclipped output signal

125

THD+N

Total harmonic distortion + noise

1 W

0.05

Output integrated noise

A-weighted

260

SNR

Signal-to-noise ratio(1)

A-weighted

100

DNR

Dynamic range

A-weighted

100

Pidle

Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching

(2)

2.3

(1)

SNR is calculated relative to 1% THD+N output level.

(2)

Actual system idle losses are affected by core losses of output inductors.

ELECTRICAL CHARACTERISTICS

PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as reference

VREG

VDD = 12 V

3.3

3.6

node

VI_CM

Analog comparator reference node

1.5

1.75

1.9

Operating, 50% duty cycle

22.5

IVDD

VDD supply current

Idle, reset mode

22.5

50% duty cycle

IGVDD_x

Gate-supply current per half-bridge

Reset mode

1.5

50% duty cycle without output filter or load

IPVDD_x

Half-bridge idle current

Reset mode, no switching

610

ANALOG INPUTS

RIN

Input resistance

READY = HIGH

Ω

VIN

Maximum input voltage swing

IIN

Maximum input current

342

Voltage gain (VOUT/VIN)

OSCILLATOR

Nominal, master mode

3.85

4.15

fOSC_IO+

AM1, master mode

FPWM × 10

3.15

3.33

3.5

MHz

AM2, master mode

2.6

3.35

VIH

High-level input voltage

1.86

VIL

Low-level input voltage

1.45

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

120

200

Ω

TJ = 25°C, includes metallization resistance,

RDS(on)

GVDD = 12 V

Drain-to-source resistance, high side (HS)

120

200

Ω

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