SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

5 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

[1]

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

[2]

In Sleep mode, XTAL2 is left floating.

6.

Functional description

The SC16C751B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C751B is fabricated with an advanced CMOS process to achieve low

drain power and high speed requirements.

The SC16C751B is an upward solution that provides 64 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The

SC16C751B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C751B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware flow control is uniquely

provided for maximum data throughput performance, especially when operating in a

multi-channel environment. The combination of the above greatly reduces the bandwidth

requirement of the external controlling CPU, increases performance, and reduces power

consumption.

The SC16C751B is capable of operation up to 5 Mbit/s with an 80 MHz external clock

input (at 5 V).

The rich feature set of the SC16C751B is available through internal registers. Automatic

hardware flow control, selectable transmit and receive FIFO trigger level, selectable TX

and RX baud rates, modem interface controls, and a Sleep mode are some of these

features.

6.1 Internal registers

The SC16C751B provides 12 internal registers for monitoring and control. These registers

are shown in Table 3. These twelve registers are similar to those already available in the

standard 16C550. These registers function as data holding registers (THR/RHR), interrupt

IOW9

I

Write input. When IOW is active (LOW) and while the UART is

selected, the CPU is allowed to write control words or data into a

selected UART register.

XTAL1

7

I

Crystal connection or External clock input.

XTAL2[2]

8O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

Table 2.

Symbol

Pin

Type

Description