SC16C751B datasheet(6/32 Pages) NXP

6 / 32 page

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

6 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and

control registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessible

Scratchpad Register (SPR). Register functions are more fully described in the following

paragraphs.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

6.2 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

trigger level has not been reached.

Table 3.

Internal registers decoding

READ mode

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)[2]

LSB of Divisor Latch

MSB of Divisor Latch

Table 4.

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS

Assert RTS

16-byte FIFO

64-byte FIFO

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