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SC16C751B Datasheet(PDF) 13 Page - NXP Semiconductors |
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SC16C751B Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 32 page ![]() SC16C751B_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 October 2008 13 of 32 NXP Semiconductors SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. • FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. • The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C751B in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. • LSR[4:1] will provide the type of errors encountered, if any. • LSR[5] will indicate when the transmit FIFO is empty. • LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. • LSR[7] will indicate any FIFO data errors. 0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. logic 0 = disable the receiver ready interrupt (normal default condition) logic 1 = enable the receiver ready interrupt Table 7. Interrupt Enable Register bits description …continued Bit Symbol Description |
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