LM3402 datasheet(12/18 Pages) NSC

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Dimming

The DIM pin of the LM3402/04 is a TTL compatible input for

low frequency pulse width modulation (PWM) dimming of the

LED current. Depending on the application, a contrast ratio

greater than what the LM3402/04 internal DIM circuitry can

provide might be needed. This demonstration board comes

with external circuitry that allows for dimming contrast ratios

greater than 50k:1

LM3402 / 04 DIM Pin Operation

To fully enable and disable the LM3402 / 04, the PWM signal

should have a maximum logic low level of 0.8V and a mini-

mum logic high level of 2.2V. Dimming frequency, f

DIM, and

duty cycle, D

DIM, are limited by the LED current rise time and

fall time and the delay from activation of the DIM pin to the

response of the internal power MOSFET. In general, f

DIM

should be at least one order of magnitude lower than the

steady state switching frequency in order to prevent aliasing.

Refer to figure 10 for illustrations. The interval t

D represents

the delay from a logic high at the DIM pin to the onset of the

output current. The quantities t

SU and tSD represent the time

needed for the LED current to slew up to steady state and

slew down to zero, respectively.

As an example, assume a DIM duty cycle D

DIM equal to 100%

(always on) and the circuit delivers 500mA of current through

the LED string. At D

DIM equal to 50% you would like exactly

½ of 500 mA of current through your LED string (250 mA).

This could only be possible if there were no delays (t

D) be-

tween the on/off DIM signal and the on/off of the LED current.

The rise and fall times (t

SU and tSD) of the LED current would

also need to be eliminated. If we can reduce these times, the

linearity between the PWM signal and the average current will

be realized.

30061652

FIGURE 10. Contrast Ratio Definitions

Contrast Ratio Definition

Contrast Ratio (CR) = 1/D

MIN

MIN = (tD + tSU) x fDIM

30061653

FIGURE 11. t

D & tSU (DIM Pin)

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