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68HC705PD6 Datasheet(PDF) 76 Page - Motorola, Inc |
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68HC705PD6 Datasheet(HTML) 76 Page - Motorola, Inc |
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76 / 165 page  GENERAL RELEASE SPECIFICATION July 7, 1997 MOTOROLA TIMER SYSTEM MC68HC05PD6 9-4 REV 1.1 Figure 9-3. Timer State Timing Diagram for Reset Figure 9-4. Timer State Timing Diagram for Timer Overflow $FFFC $FFFD $FFFE $FFFF Internal Processor Clock Internal Reset T00 T01 T10 T11 Counter (16 Bit) RESET (External, LVR or POR) Internal Timer Clocks NOTE: The Counter Register and Timer Control Register are the only ones affected by RESET $FFFE $0000 $0001 $0002 Internal Processor Clock T00 T01 T10 T11 Counter (16 Bit) Timer Overflow Flag (TOF) Internal Timer Clocks NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by read of the timer status register during the internal processor clock high time followed by a read of the counter low register. $FFFF |
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