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68HC705PD6 Datasheet(PDF) 83 Page - Motorola, Inc

Part # 68HC705PD6
Description  SPECIFICATION (General Release)
PDF  165 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

68HC705PD6 Datasheet(HTML) 83 Page - Motorola, Inc

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July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
TIMER SYSTEM
MOTOROLA
REV 1.1
9-11
OLVL
The value of the output level (OLVL) bit is clocked into the output level register
by the next successful output compare and will appear at TCMP pin. This bit
and the output level register are cleared by reset.
0 =
low output
1 =
high output
9.1.5 Timer Status Register (TSR)
The timer status register is a read-only register and is illustrated below followed by
a definition of each bit. Refer to timing diagrams shown in Figure 9-3, Figure 9-4
and Figure 9-5 for timing relationship to the timer status register bits.
ICF
The input capture flag (ICF) is set when a proper edge has been sensed by the
input capture edge detector. It is cleared by a processor access of the timer
status register (with ICF set) followed by accessing the low byte ($15) of the
input capture register. Reset does not affect the input compare flag.
OC1F
The output compare flag (OC1F) is set when the output compare register
contents matches the contents of the free running counter. The OC1F is
cleared by accessing the timer status register (with OC1F set) and then
accessing the low byte ($17) of the output compare register. Reset does not
affect the output compare flag.
TOF
The timer overflow flag (TOF) bit is set by transition of the free run from $FFFF
to $0000. It is cleared by accessing the timer status register (with TOF set)
followed by an access of the free running counter least significant byte ($19).
Reset does not affect the TOF bit.
Accessing the timer status register satisfies the first condition required to clear
status bits. The remaining step is to access the register corresponding to the
status bit.
A problem can occur when using the timer overflow function and reading the free-
running counter at random times to measure an elapsed time. Without
incorporating the proper precautions into software, the timer overflow flag could
X
7
X
X
00000
6543210
0
0
0
0
0
TOF
OC1F
ICF
W
R
TSR
$0013
reset



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