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P9S12XEP100F1MVLR Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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P9S12XEP100F1MVLR Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 1324 page ![]() Chapter 1 Device Overview MC9S12XE-Family MC9S12XE-Family Reference Manual , Rev. 1.21 86 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 1.7 ADC0 Configuration 1.7.1 External Trigger Input Connection The ADC module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ADC conversion to external trigger events. Table 1-17 shows the connection of the external trigger inputs. Consult the ATD block description for information about the analog-to-digital converter module. ATD block description refererences to freeze mode are equivalent to active BDM mode. 1.7.2 ADC0 Channel[17] Connection Further to the 16 externally available channels, ADC0 features an extra channel[17] that is connected to the internal temperature sensor at device level. To access this channel ADC0 must use the channel encoding SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to 1.10.1 Temperature Sensor Configuration 1.8 ADC1 External Trigger Input Connection The ADC module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger feature allows the user to synchronize ADC conversion to external trigger events. Table 1- 18 shows the connection of the external trigger inputs. Consult the ADC block description for information about the analog-to-digital converter module. ADC block description refererences to freeze mode are equivalent to active BDM mode. Table 1-17. ATD0 External Trigger Sources External Trigger Input Connectivity ETRIG0 Pulse width modulator channel 1 ETRIG1 Pulse width modulator channel 3 ETRIG2 Periodic interrupt timer hardware trigger 0 ETRIG3 Periodic interrupt timer hardware trigger 1 Table 1-18. ATD1 External Trigger Sources External Trigger Input Connectivity ETRIG0 Pulse width modulator channel 1 ETRIG1 Pulse width modulator channel 3 ETRIG2 Periodic interrupt timer hardware trigger 0 ETRIG3 Periodic interrupt timer hardware trigger 1 |
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