P9S12XEP100F1MVLR datasheet(92/1324 Pages) FREESCALE

92 / 1324 page

Chapter 2 Port Integration Module (S12XEPIMV1)

MC9S12XE-Family Reference Manual , Rev. 1.21

Freescale Semiconductor

PE[7]

XCLKS 2

External clock selection input during RESET

Mode

dependent 4

ECLKX2

Free-running clock output at Core Clock rate (ECLK x 2)

GPIO

I/O General-purpose I/O

PE[6]

MODB 2

MODB input during RESET

TAGHI

Instruction tagging low pin

Conﬁgurable for reduced input threshold

GPIO

I/O General-purpose I/O

PE[5]

MODA 2

MODA input during RESET

Read enable signal

TAGLO

Instruction tagging low pin

Conﬁgurable for reduced input threshold

GPIO

I/O General-purpose I/O

PE[4]

ECLK

Free-running clock output at the Bus Clock rate or programmable

divided in normal modes

GPIO

I/O General-purpose I/O

PE[3]

EROMCTL 2

EROMON bit control input during RESET

LSTRB

Low strobe bar output

LDS

Lower data strobe

GPIO

I/O General-purpose I/O

PE[2]

Read/write output for external bus

Write enable signal

GPIO

I/O General-purpose I/O

PE[1]

IRQ

Maskable level- or falling edge-sensitive interrupt input

GPI

General-purpose input

PE[0]

XIRQ

Non-maskable level-sensitive interrupt input

GPI

General-purpose input

PK[7]

ROMCTL 2

ROMON bit control input during RESET

Mode

dependent 3

EWAIT

External Wait signal

Conﬁgurable for reduced input threshold

GPIO

I/O General-purpose I/O

PK[6:4]

ADDR[22:20]

mux

ACC[2:0] 3

Extended external bus address output

(multiplexed with access master output)

GPIO

I/O General-purpose I/O

PK[3:0]

ADDR[19:16]

mux

IQSTAT[3:0] 3

Extended external bus address output

(multiplexed with instruction pipe status bits)

GPIO

I/O General-purpose I/O

Port

Pin Name

Pin Function

& Priority(1)

I/O

Description

Pin Function

after Reset

P9S12XEP100F1MVLR Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc

P9S12XEP100F1MVLR Datasheet(HTML) 92 Page - Freescale Semiconductor, Inc

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