P9S12XEP100F1MVLR datasheet(89/1324 Pages) FREESCALE

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MC9S12XE-Family Reference Manual , Rev. 1.21

Freescale Semiconductor

Chapter 2

Port Integration Module (S12XEPIMV1)

2.1

Introduction

2.1.1

Overview

The S12XE Family Port Integration Module establishes the interface between the peripheral modules

including the non-multiplexed External Bus Interface module (S12X_EBI) and the I/O pins for all ports.

It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.

This document covers:

•

Port A and B used as address output of the S12X_EBI

•

Port C and D used as data I/O of the S12X_EBI

•

Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs

•

Port K associated with address output and control signals of the S12X_EBI

•

Port T associated with 1 ECT module

•

Port S associated with 2 SCI and 1 SPI modules

•

Port M associated with 4 MSCAN and 1 SCI module

•

Port P connected to the PWM and 2 SPI modules - inputs can be used as an external interrupt source

•

Port H associated with 4 SCI modules - inputs can be used as an external interrupt source

•

Port J associated with 1 MSCAN, 1 SCI, 2 IIC modules and chip select outputs - inputs can be used

as an external interrupt source

•

Port AD0 and AD1 associated with two 16-channel ATD modules

•

Port R associated with 1 standard timer (TIM) module

•

Port L associated with 4 SCI modules

Table 2-1. Revision History

Revision

Number

Revision Date

Sections

Affected

Description of Changes

V01.17

02 Apr 2008

• Corrected reduced drive strength to 1/5

• Separated PE1,0 bit descriptions from other PE GPIO

V01.18

25 Nov 2008

2.3.19/120

2.4.3.4/181

• Corrected alternative functions on Port K (ACC[2:0])

• Corrected functions on PE[5] (MODB) and PE[2] (WE)

V01.19

18 Dec 2009

• Added function independency to reduced drive and wired-or bit

descriptions

• Minor corrections

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