50

60

70

80

90

100

110

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

G035

65

67

69

71

73

75

77

79

81

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

G036

CLKP

CLKM

ADS548x

0.1

F

m

Clock

Source

S0194-03

ADS5484

ADS5485

SFDR

SNR

vs

vs

CLOCK AMPLITUDE

CLOCK AMPLITUDE

Figure 39.

Figure 40.

For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The

differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a

differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications

because the board level clock jitter is superior.

The sampling process is more sensitive to jitter using high analog input frequencies or slow clock frequencies.

Large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the ADC clock

Figure 41 demonstrates a recommended method for converting a single-ended clock source into a differential

clock; it is similar to the configuration found on the evaluation board and was used for much of the

characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.

Figure 41. Differential Clock

The common-mode voltage of the clock inputs is set internally to ~2 V using internal 0.5-k

Ω resistors. It is

recommended to use ac coupling, but if this scheme is not possible, the ADS548x features good tolerance to

clock common-mode variation (as shown in Figure 42 and Figure 43). The internal ADC core uses both edges of

the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance

degradation as a result of duty cycle can be seen in Figure 44.

Copyright © 2008–2009, Texas Instruments Incorporated

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