Clock Common-Mode Voltage − V

50

60

70

80

90

100

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G037

30.13 MHz

230.53 MHz

100.33 MHz

69.59 MHz

CLK = 200 MSPS

Clock Common-Mode Voltage − V

66

67

68

69

70

71

72

73

74

75

76

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G038

CLK = 200 MSPS

30.13 MHz

100.33 MHz

69.59 MHz

230.53 MHz

Clock Duty Cycle − %

50

55

60

65

70

75

80

85

90

95

30

35

40

45

50

55

60

65

70

G039

170 MSPS (ADS5484)

200 MSPS (ADS5485)

30 MHz

230 MHz

130 MHz

ADS5484

ADS5485

Figure 42. SFDR versus Clock Common-Mode

Figure 43. SNR versus Clock Common-Mode

Voltage

Voltage

Figure 44. SFDR vs Clock Duty Cycle

The ADS5484 is capable of achieving 75.7 dBFS SNR at 130 MHz of analog input frequency. In order to achieve

the SNR at 130 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 184 fsec in order

for the total rms jitter to be 201 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum

recommended rms clock jitter as a function of analog input frequency for the ADS5484 is provided in Table 3.

The equations used to create the table are presented and can be used to estimate required clock jitter for

virtually any pipeline ADC, but in particular, the ADS5481/5482/5483/5484/5485 family.

Table 3. Recommended Approximate RMS Clock Jitter for ADS5484

ANALOG INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM CLOCK JITTER

(MHz)

(dBc)

(fsec rms)

(fsec rms)

10

76.8

2301

2299

30

75.9

851

847

70

75.7

373

364

130

75.7

201

184

170

75.6

155

133

230

74.9

124

95

24

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