15kW

20kW

473.5pF

ChargePump

Output

VCOControl

CDCM61002

SCAS870D – FEBRUARY 2009 – REVISED JULY 2010

www.ti.com

For example, if an application requires less than ±50 ppm frequency error and a crystal with less than ±50 ppm

CDCM61002 to ensure that the sum of the crystal stray capacitance and board parisitic capacitance is less than

the calculated 5 pF.

Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to

locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in the

oscillator circuit are a very common source of problems. Do not route other signals across the oscillator circuit.

Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and

noise coupling. Avoid the use of vias; if the routing becomes very complex, it is much better to use 0-

Ω resistors

as bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the

ground plane. Do not share ground connections; instead, make a separate connection to ground for each

component that requires grounding. If possible, place multiple vias in parallel for each connection to the ground

plane. Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel

with the crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less

than 5 pF total under all circumstances to ensure proper crystal oscillation. Be sure to take into account both

PCB and crystal stray capacitance.

Table 9 lists several recommended crystals and the respective manufacturer of each.

Table 9. Recommended Crystal Manufacturers

MANUFACTURER

PART NUMBER

Vectron

VXC1-1133

Fox

218-3

Saronix

FP2650002

Phase Frequency Detector (PFD)

The PFD takes inputs from the input interface and the feedback divider and produces an output that depends on

the phase and frequency differences between the two inputs. The allowable range of frequencies at the PFD

inputs is 21.875 MHz to 28.47 MHz.

Charge Pump (CP)

The charge pump is controlled by the PFD, which dictates either to pump up or down in order to charge or

discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then

converted to a voltage that drives the control voltage node of the internal VCO through the on-chip loop filter. The

charge pump current is preset to 224 mA and cannot be changed.

On-Chip PLL Loop Filter

Figure 16 shows the on-chip active loop filter topology implemented in the device. This design corresponds to a

PLL bandwidth of 400 kHz for a PFD in the range of 21.875 MHz to 28.47 MHz, and a charge pump current of

224 mA.

Figure 16. On-Chip PLL Loop Filter Topology

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