Analog

Supply

C

0.1 mF(x3)

C

10 F

m

C

10 F

m

C

0.1 F(x3)

m

FerriteBead

Board/

Supply

Output/Input

CDCM61002

LVPECL

82 W

82 W

130 W

130 W

V

CC_OUT

V

CC_OUT

CDCM61002

LVPECL

50 W

50 W

150 W

150 W

V

BB

CDCM61002

www.ti.com

SCAS870D – FEBRUARY 2009 – REVISED JULY 2010

Figure 19 shows a general recommendation for decoupling the power supply.

Figure 19. Recommended Power-Supply Decoupling

Output Termination

The CDCM61002 is a 3.3-V clock driver with the following output options: LVPECL, LVDS, or LVCMOS.

LVPECL Termination

The CDCM61002 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required

to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL is

50

is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled cases, as shown in

Figure 20 and Figure 21. It is recommended to place all resistive components close to either the driver end or the

receiver end. If the supply voltage of the driver and receiver are different, ac-coupling is required.

Figure 20. LVPECL Output DC Termination

Figure 21. LVPECL Output AC Termination

Copyright © 2009–2010, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Link(s): CDCM61002