0,3mm

(typ)

0,7mm

(typ)

3,0mm

(min)

CDCM61002

SCAS870D – FEBRUARY 2009 – REVISED JULY 2010

www.ti.com

Thermal Management

Power consumption of the CDCM61002 can be high enough to require attention to thermal management. For

reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as

The device package has an exposed pad that provides the primary heat removal path as well as an electrical

grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal land

pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A

recommended land and via pattern is shown in Figure 18.

Figure 18. Recommended PCB Layout for CDCM61002

Power-Supply Filtering

PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically

increase the jitter of the PLL. This characteristic is especially true for analog-based PLLs. Thus, it is essential to

reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A

PLL would have attenuated jitter as a result of power-supply noise at frequencies beyond the PLL bandwidth

because of attenuation by the loop response.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system

against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required

by the device and should have low equivalent series resistance (ESR). To properly use these bypass capacitors,

they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It

is recommended to add as many high-frequency (for example, 0.1-mF) bypass capacitors as there are supply

pins in the package.

The CDCM61002 power-supply requirements can be grouped into two sets: the analog supply line and the

output/input supply line. The analog supply line consists of the following power-supply pins on the CDCM61002:

VCC_PLL1, VCC_PLL2, and VCC_VCO. These pins can be shorted together. The output/input supply line

consists of the VCC_OUT and the VCC_IN power-supply pins on the CDCM61002. These pins can be shorted

together. Inserting a ferrite bead between the analog supply line and the output/input supply line isolates the

high-frequency switching noises generated by the device input and outputs, preventing them from leaking into

the sensitive analog supply line. Choosing an appropriate ferrite bead with very low dc resistance is important

because it is imperative to provide adequate isolation between the sensitive analog supply line and the other

board supply lines, and to maintain a voltage at the analog power-supply pins of the CDCM61002 that is greater

than the minimum voltage required for proper operation.

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