TPS780 datasheet(16/27 Pages) TI

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BOARD LAYOUT RECOMMENDATIONS TO

INPUT AND OUTPUT CAPACITOR

TPS780 Series

SBVS083C – JANUARY 2007 – REVISED MAY 2008 ....................................................................................................................................................... www.ti.com

The total system power savings is outlined in Table 4,

capacitor may be necessary if large, fast rise-time

Table 5, and Table 6. In Table 4, the MSP430 power

load transients are anticipated, or if the device is not

savings are calculated for various MSP430 devices

located near the power source. If source impedance

using a TPS780 series with integrated DVS versus a

is not sufficiently low, a 0.1

µF input capacitor may be

standard ultralow IQ LDO without DVS. In Table 5, the

necessary to ensure stability.

TPS780 series quiescent power is calculated for a VIN

The TPS780 is designed to be stable with standard

of 4.2V, with the same VIN used for the ultralow IQ

ceramic capacitors with values of 1.0

µF or larger at

LDO. Quiescent power dissipation in an LDO is the

the output. X5R- and X7R-type capacitors are best

VIN voltage times the ground current, because zero

because they have minimal variation in value and

load is applied. After the dissipation power is

ESR over temperature. Maximum ESR should be less

calculated for the individual LDOs in Table 5, simple

than 1.0

Ω. With tolerance and dc bias effects, the

subtraction outputs the LDO power savings using the

minimum capacitance required to ensure stability is

TPS780 series. Table 6 calculates the total system

µF.

power savings using a TPS780 series LDO in place

of an ultralow IQ 1.2µA LDO in an MSP430F1121

application. There are many different versions of the

IMPROVE PSRR AND NOISE PERFORMANCE

MSP430. Actual power savings will vary depending

on the selected device.

To improve ac performance (such as PSRR, output

noise, and transient response), it is recommended

that the printed circuit board (PCB) be designed with

REQUIREMENTS

separate ground planes for VIN and VOUT, with each

ground plane connected only at the GND pin of the

Although an input capacitor is not required for

device. In addition, the ground connection for the

stability, it is good analog design practice to connect

output capacitor should connect directly to the GND

a 0.1

µF to 1.0µF low equivalent series resistance

pin of the device. High ESR capacitors may degrade

(ESR) capacitor across the input supply near the

PSRR.

regulator. This capacitor counteracts reactive input

sources and improves transient response, noise

rejection,

and

ripple

rejection.

higher-value

Table 4. DVS MSP430 Power Savings with the TPS780 Series on selected MSP430 Devices

LPM3 AT VCC = 3V,

LPM3 AT VCC = 3.0V

LPM3 AT VCC =

LPM3 AT VCC = 2.2V

× I

2.2V, IQ

× I

µW SAVINGS

DEVICE

(

µA)

(

µW)

(

µA)

(

µW)

USING ONLY DVS

MSP430F1121

1.6

4.8

0.7

1.5

3.3

MSP430F149

1.6

4.8

0.9

2.0

2.8

MSP430F2131

0.9

2.7

0.7

1.5

1.2

MSP430F249

1.0

3.0

0.9

2.0

1.0

MSP430F413

0.9

2.7

0.7

1.5

1.2

MSP430F449

1.6

4.8

1.1

2.4

Table 5. Typical Ultralow IQ LDO Quiescent Power Dissipation Versus the TPS780 Series

MSP430 SYSTEM

TYPICAL ULTRALOW IQ

TPS780 SERIES

TPS780 SERIES AT

POWER SAVINGS

TYPICAL ULTRALOW IQ LDO AT +25°C AMBIENT

TYPICAL IQ AT +25°C

+25C AMBIENT, POWER

USING THE TPS780

LDO AT +25

°C AMBIENT

POWER DISSIPATION

AMBIENT

DISSIPATION

SERIES

QUIESCENT POWER

IQ × VIN = 4.2V

TPS780 IQ

IQ × VIN = 4.2V

DISSIPATION SAVINGS

(

µA)

(

µW)

(

µA)

(

µW)

(

µW)

1.20

5.04

0.42

1.76

3.28

Table 6. Total System Power Dissipation

TOTAL SYSTEM POWER IN

LDO DISSIPATION

MSP430 DISSIPATION

SLEEP MODE 3

Typical 1.2

µA LDO, no DVS

5.04

µW

4.8

µW(1)

9.84

µW

TPS780 Series with DVS

1.76

µW

1.5

µW(1)

3.26

µW

(1)

Value taken from Table 4 and relative to the MSP430F1121.

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