AM1707 datasheet(69/199 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

6.11.6 EMIFA Electrical Data/Timing

The following assume testing over recommended operating conditions.

Table 6-20. EMIFA SDRAM Interface Timing Requirements

No.

PARAMETER

MIN

MAX

UNIT

Input setup time, read data valid on EMA_D[15:0] before EMA_CLK

tsu(DV-CLKH)

1.3

rising

Input hold time, read data valid on EMA_D[15:0] after EMA_CLK

th(CLKH-DIV)

1.5

rising

Table 6-21. EMIFA SDRAM Interface Switching Characteristics

No.

PARAMETER

MIN

MAX

UNIT

tc(CLK)

Cycle time, EMIF clock EMA_CLK

tw(CLK)

Pulse width, EMIF clock EMA_CLK high or low

td(CLKH-CSV)

Delay time, EMA_CLK rising to EMA_CS[0] valid

toh(CLKH-CSIV)

Output hold time, EMA_CLK rising to EMA_CS[0] invalid

td(CLKH-DQMV)

Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid

toh(CLKH-DQMIV)

Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid

Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]

td(CLKH-AV)

valid

Output hold time, EMA_CLK rising to EMA_A[12:0] and

toh(CLKH-AIV)

EMA_BA[1:0] invalid

td(CLKH-DV)

Delay time, EMA_CLK rising to EMA_D[15:0] valid

toh(CLKH-DIV)

Output hold time, EMA_CLK rising to EMA_D[15:0] invalid

td(CLKH-RASV)

Delay time, EMA_CLK rising to EMA_RAS valid

toh(CLKH-RASIV)

Output hold time, EMA_CLK rising to EMA_RAS invalid

td(CLKH-CASV)

Delay time, EMA_CLK rising to EMA_CAS valid

toh(CLKH-CASIV)

Output hold time, EMA_CLK rising to EMA_CAS invalid

td(CLKH-WEV)

Delay time, EMA_CLK rising to EMA_WE valid

toh(CLKH-WEIV)

Output hold time, EMA_CLK rising to EMA_WE invalid

tdis(CLKH-DHZ)

Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated

tena(CLKH-DLZ)

Output hold time, EMA_CLK rising to EMA_D[15:0] driving

Table 6-22. EMIFA Asynchronous Memory Timing Requirements(1)

No.

PARAMETER

MIN

NOM

MAX

UNIT

READS and WRITES

tc(CLK)

Cycle time, EMIFA module clock

Pulse duration, EM_WAIT assertion and

tw(EM_WAIT)

deassertion

READS

Setup time, EM_D[15:0] valid before EM_OE

tsu(EMDV-EMOEH)

high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

Setup Time, EM_WAIT asserted before end of

tsu (EMOEL-EMWAIT)

4E+3

Strobe Phase(2)

WRITES

(1)

E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when

SYSCLK3 is selected and set to 100MHz, E=10ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Peripheral Information and Electrical Specifications

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