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ISO1050 Datasheet(PDF) 3 Page - Texas Instruments |
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ISO1050 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 24 page ![]() ISO1050 www.ti.com SLLS983C – JUNE 2009 – REVISED JULY 2010 DEVICE SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Total loop delay, driver input to receiver output, Recessive to tloop1 See Figure 9 112 150 210 ns Dominant Total loop delay, driver input to receiver output, Dominant to tloop2 See Figure 9 112 150 210 ns Recessive DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CANH 2.9 3.5 4.5 VO(D) Bus output voltage (Dominant) See Figure 1 and Figure 2, VI = 0 V, RL = 60Ω V CANL 0.8 1.2 1.5 VO(R) Bus output voltage (Recessive) See Figure 1 and Figure 2, VI = 2 V, RL= 60Ω 2 2.3 3 V See Figure 1, Figure 2 and Figure 3, VI = 0 V, 1.5 3 RL = 60Ω VOD(D) Differential output voltage (Dominant) V See Figure 1, Figure 2, and Figure 3 VI = 0 V, 1.4 3 RL = 45Ω, Vcc > 4.8V See Figure 1 and Figure 2, VI = 3 V, RL = 60Ω –0.12 0.012 VOD(R) Differential output voltage (Recessive) V VI = 3 V, No Load –0.5 0.05 VOC(D) Common-mode output voltage (Dominant) 2 2.3 3 See Figure 8 V VOC(pp) Peak-to-peak common-mode output voltage 0.3 IIH High-level input current, TXD input VI at 2 V 5 mA IIL Low-level input current, TXD input VI at 0.8 V –5 mA IO(off) Power-off TXD leakage current VCC1, VCC2 at 0 V, TXD at 5 V 10 mA See Figure 11, VCANH = –12 V, CANL Open –105 –72 See Figure 11, VCANH = 12 V, CANL Open 0.36 1 IOS(ss) Short-circuit steady-state output current mA See Figure 11, VCANL =–12 V, CANH Open –1 –0.5 See Figure 11, VCANL = 12 V, CANH Open 71 105 CO Output capacitance See receiver input capacitance CMTI Common-mode transient immunity See Figure 13, VI = VCC or 0 V 25 50 kV/ms DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, recessive-to-dominant output 31 74 110 tPHL Propagation delay time, dominant-to-recessive output 25 44 75 See Figure 4 ns tr Differential output signal rise time 20 50 tf Differential output signal fall time 20 50 tdom Dominant time-out ↓ CL=100 pF, See Figure 10 300 450 700 ms Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ISO1050 |
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