EP3SL340 datasheet(42/341 Pages) ALTERA

42 / 341 page

1–32

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2

Altera Corporation

Figure 1–4 shows the setup and hold timing diagram for input registers.

For output timing, different I/O standards require different baseline loading

techniques for reporting timing delays. Altera characterizes timing delays with the

required termination for each I/O standard and with 0 pF (except for PCI and PCI-X,

which use 10 pF) loading. The timing is specified up to the output pin of the FPGA

device. The Quartus II software calculates I/O timing for each I/O standard with a

default baseline loading as specified by the I/O standards.

The following measurements are made during device characterization. Altera

measures clock-to-output delays (tco) at worst-case process, minimum voltage, and

maximum temperature (PVT) for default loading conditions listed in Table 1–37 on

page 1–34. The following equation describes clock-pin-to-output-pin timing for

Stratix III devices.

The tco from the clock pin to the I/O pin =

+ delay from the clock pad to the I/O output register

+ IOE output register clock-to-output delay

+ delay from the output register to the output pin

Figure 1–5 shows the output register clock to output timing diagram.

Simulation using IBIS models is required to determine the delays on the PCB traces in

addition to the output pin delay timing reported by the Quartus II software and the

timing model in the Stratix III Device Handbook. Perform the following steps:

1. Simulate the output driver of choice into the generalized test setup using values

from Table 1–37.

2. Record the time to VMEAS at the far end of the PCB trace.

3. Simulate the output driver of choice into the actual PCB trace and load using the

appropriate IBIS model or capacitance value to represent the load.

4. Record the time to VMEAS at the far end of the PCB trace.

Figure 1–4. Input Register Setup and Hold Timing Diagram

Input Data Delay

Input Clock Delay

micro tsu

micro th

Figure 1–5. Output Register Clock to Output Timing Diagram

Output Register to

output pin delay

Clock

Datain

Clock pad to output

Output Register

micro tCO

Output

EP3SL340 Datasheet(PDF) 42 Page - Altera Corporation

EP3SL340 Datasheet(HTML) 42 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL