Preliminary
6-39
RF2640
Rev A3 010717
6
Evaluation Board Schematic
RF=836MHz, LO=1016MHz
(Download Bill of Materials from www.rfmd.com.)
Pin
Function
Description
Interface Schematic
1IF+
Balanced IF input pin. This pin is internally DC-biased and should be
DC-blocked if connected to a device with a DC level present. For single-
ended input operation, one pin is used as an input and the other IF
input is AC-coupled to ground. The single-ended input impedance is
50
Ω.
2/26/1997
2IF-
Same as pin 1, except complementary input.
3GND1
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
4LO+
Single-ended LO input pin. This pin is internally DC-biased and should
be DC-blocked if connected to a device with a DC level present. The
single-ended input impedance is 50
Ω.
5GND2
Same as pin 3, except complementary input.
6RF OUT
RF Output Pin. The output impedance is 50
Ω.
7RF GND
This pin requires a small inductance to ground to optimize the gain and
third order intercept point. See Evaluation Board Layout. The trace
length on the board is approximately 65mils.
8GND3
Same as pin 7.
9PD
Power down control. When logic “high” (between 1.2V and 1.8V) the
device is active and all circuits are operating. When logic “low”
(between 0.0V and 0.6V) the device is inactive and all circuits are
turned off.
10
VCC
Supply Voltage pin. External bypassing is required. External RF, LO,
and IF bypassing is required. The trace length between the pin and the
bypass capacitors should be minimized. The ground side of the bypass
capacitors should connect immediately to ground plane.
1
2
3
4
5
10
9
8
7
6
C1
1nF
C2
1nF
C3
22 pF
50
Ω µstrip
50
Ω µstrip
J1
IF IN
J2
LO IN
C3
22 pF
L1
12 nH
VCC
PD
50
Ω µstrip
VCC
J3
RF OUT
C4
1nF
C6
1nF
P1
1
2
3
P1-1
PD
GND
P1-3
VCC
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