KB8527B

1 CHIP CLP SUBSYSTEM IC

Pin No

Symbol

Description

PDR

Phase detector output terminal of the receiver at PLL.

The output is negative pulse

The output is positive pulse

The output is high impedance

45

PLL voltage reference output pin.

An internal voltage regulator provides a stable power supply voltage for the RX

and TX PLLs.

46

Power supply terminal of PLL.

47

TIF

Input terminal of TX channel counter.

AC coupling with TX VCO.

Minimum input level is 300 mVp-p ( at 60MHz ).

48