KB8527B

1 CHIP CLP SUBSYSTEM IC

PIN DESCRIPTION

Pin No

Symbol

Description

1

CO

Compressor output terminal of compandor ; connected to the splatter filter amp

input terminal.

2

PDT

Phase detector output terminal of the transmitter at PLL.

If f

the output is negative pulse

If f

the output is positive Pulse

if f

the output is High Impedance

3

4

5

LDT/

CDO

Ground.

Ground of logic section at PLL.

LBD

Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ).

During the normal operation, output level is low, but it is high at low battery

detection. As this pin is an open collector type, it requires a pull - up resister.

These pins are serial interface terminals for programming reference counter,

auxiliary reference counter, TX channel counter, RX channel counter and control

block that controls internal each block with test mode and power saving mode.

CLK

7

8

9

DATA

EN

10

This pin bypasses AC elements at the feedback loop which come from the SUM

amp block of COMPRESSOR. A capacitor should be connected between this ter-

minal and GND. ( C = 2.2 uF )

11

AGIC

Input terminal of Splatter filter amp.

SFI

SFO

Output terminal of Splatter filter amp.

LDT : Output terminal of transmitter lock detector in PLL block. Output is low

if PLL is in lock state and is high if PLL is in unlock state.

CDO : As an output terminal of the carrier detector buffer, connected to (RSSI )

terminal of MICOM. This pin outputs the contents of Meter Driver buffer

which is turned on / off, according to the signal level detected by Meter

Driver.

6