LTC2463CDDPBF datasheet(12/20 Pages) LINER

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LTC2461/LTC2463

24613f

APPLICATIONS INFORMATION

The LTC2461 (single-ended input) output code is a direct

binary encoded result, see Table 1.

Data Input Format

After a START condition, the master sends a 7-bit ad-

dress followed by a read/write request (R/W) bit. The

R/W bit is 0 for a write. The data input word is 4 bits long

and consists of two enable bits (EN1 and EN2) and two

programming bits (SPD and SLP), see Figure 5b. EN1 is

applied to the ﬁrst rising edge of SCL after a valid write

address is acknowledged. Programming is enabled by

setting EN1 = 1 and EN2 = 0.

The speed bit (SPD) is only used by the LTC2461. In the

default mode, SPD = 0, the output rate is 60Hz and con-

tinuous background offset calibration is not performed. By

changing the SPD bit to 1, background offset calibration

is performed and the output rate is reduced to 30Hz. The

LTC2463 data output rate is always 60Hz and background

offset calibration is performed (SPD = don’t care).

The sleep bit (SLP) is used to power down the on chip

reference. In the default mode, the reference remains

powered up even when the ADC is powered down. If the

SLP bit is set HIGH, the reference will power down after

Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463

SDA

SCL

EN1

EN2

SPD

SLP

SLEEP

START BY

MASTER

DATA INPUT

23456

…

7-BIT ADDRESS

ACK BY

LTC2461/LTC2463

ACK BY

LTC2461/LTC2463

24613 F03

Table 1. LTC2461/LTC2463 Output Data Format

SINGLE ENDED INPUT VIN

(LTC2461)

DIFFERENTIAL INPUT VOLTAGE

VIN+ – VIN– (LTC2463)

D15

(MSB)

D14

D13

D12...D2

(LSB)

CORRESPONDING

DECIMAL VALUE

≥VREF

65535

VREF – 1LSB

65534

0.75 • VREF

0.5 • VREF

49152

0.75 • VREF – 1LSB

0.5 • VREF – 1LSB

49151

0.5 • VREF

32768

0.5 • VREF – 1LSB

–1LSB

32767

0.25 • VREF

–0.5 • VREF

16384

0.25 • VREF – 1LSB

–0.5 • VREF – 1LSB

16383

≤ –VREF

000

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