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PT6554 Datasheet(PDF) 6 Page - Princeton Technology Corp |
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PT6554 Datasheet(HTML) 6 Page - Princeton Technology Corp |
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6 / 30 page ![]() PT6554 V1.4 6 June 2010 PIN DESCRIPTION Pin Pin No. Function Active I/O Handling when unused SG1/P1 to SG4/P4 SG5 to SG39 1 to 4 5 to 39 Segment outputs for displaying the display data transferred by serial data input. The SG1/P1 to SG4/P4 pins can be used as general-purpose output ports under serial data control. - O Open COM1 COM2 COM3 COM4 40 41 42 43 Common driver outputs The frame frequency fO is given by: fO=(fosc/512)Hz - O Open KS1/SG40, KS2/SG41, KS3 to KS6 44 45 46 to 49 Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to from a key matrix. The KS1/SG40 and KS2/SG41 pins can be used as segment outputs when so specified by the control data - O Open KI1to KI5 50 to 54 Key scan inputs. These pins have built-in pull-down resistors. H I GND OSC 60 Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. - I/O VDD CE CLK DI 62 63 64 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE: Chip enable CLK: Synchronization clock DI: Transfer data DO: Output data H - - I I I GND DO 61 O Open TEST 55 This pin must be connected to ground. - I - VDD1 57 Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VDD1 when a 1/2 bias drive scheme is used. - I Open VDD2 58 Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VDD1 when a 1/2 bias drive scheme is used. - I Open VDD 56 Power supply connection. Provide a voltage of between 4.5 and 6.0V - - - VSS 59 Power supply connection. Connect to ground. - - - |
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