PT6554

V1.4

13

June 2010

SERIAL DATA OUTPUT

CASE 1: CLK IS TERMINATED AT “LOW” LEVEL

Notes:

1. Address: 43H

2. Key Output Data Bits: KD1 to KD30

3. Sleep Acknowledge Bit: SA

4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge

Bit (SA) will not be valid.

CASE 2: CLK IS TERMINATED AT “HIGH” LEVEL

Notes

:

1. Address: 43H

2. Key Output Data Bits: KD1 to KD30

3. Sleep Acknowledge Bit: SA

4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge

Bit (SA) will not be valid.