LM2759 datasheet(4/14 Pages) NSC

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Limits in standard typeface are for T

J = 25°C. Limits in boldface type apply over the full operating junction temperature range (-30°

≤ T

J ≤ +125 °C). Unless otherwise noted, specifications apply to the LM2759 Typical Application Circuit (pg.1) with VIN = 3.6V,

TX = 0V, VSTROBE = 0V, CIN = C1 = C2 = 2.2 µF, COUT = 4.7 µF. (Note 10)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

I2C Compatible Interface Voltage Specifications (SCL, SDA).

Input Logic Low “0”

2.7V

≤ V

IN ≤ 5.5V

0.72

Input Logic High “1'

2.7V

≤ V

IN ≤ 5.5V

1.25

Output Logic Low “0”

LOAD = 3 mA

300

I2C Compatible Interface Timing Voltage Specifications (SCL, SDA) (Note 11)

SCL (Clock Period)

2.5

µs

Data in Setup Time to SCL

High

100

Data Out Stable After SCL

Low

SDA Low Setup Time to

SCL Low (Start)

100

SDA High Hold Time After

SCL High (Stop)

100

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 3: All voltages are with respect to the potential to the GND pin.

Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T

J=150°C (typ.) and disengages at TJ =

120°C (typ.).

Note 5: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN-1187.

Note 6: The Human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. (MIL-STD-883 3015.7)

Note 7: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T

A-MAX) is dependent on the maximum operation junction temperature (TJ-MAX-OP = 125ºC), the maximum power

dissipation of the device in the application (P

D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

following equation: T

A-MAX = TJ-MAX-OP - (θJA × PD-MAX).

Note 8: Junction-to-ambient thermal resistance (

JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the

JEDEC standard JESD51-7. The test board is a 4–layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane

on the board is 50 mm x 50 mm. Thickness of copper layers are 53µm/35µm/35µm/53µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still

air. Power dissipation is 1W.

The value of

JA of this product in the LLP package could fall in a range as wide as 30ºC/W to 150ºC/W (if not wider), depending on PWB material, layout, and

environmental conditions. In applications where high maximum power dissipation exists (high V

IN, high IOUT), special care must be paid to thermal dissipation

issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power

Dissipation section of this datasheet.

Note 9: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (Typ) numbers are not guaranteed, but do represent the most likely

norm. Unless otherwise specified, conditions for Typ specifications are: V

IN = 3.6V and TA = 25°C.

Note 10: C

IN, COUT, C1, C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 11: SCL and SDA should be glitch-free in order for proper brightness control to be realized.

Note 12: For input voltage below the regulation target during the gain of 1x, the output voltage will typically be equal to the input voltage.

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