EP3C55 datasheet(29/34 Pages) ALTERA

29 / 34 page

Chapter 1: Cyclone III Device Data Sheet

1–29

Glossary

Altera Corporation

Cyclone III Device Handbook, Volume 2

Receiver differential input discrete resistor (external to Cyclone III devices).

Receiver Input

Waveform

Receiver Input Waveform for LVDS and LVPECL Differential Standards.

RSKM (Receiver

input skew

margin)

HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.

RSKM = (TUI – SW – TCCS) / 2.

Single-ended

Voltage

referenced I/O

Standard

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal

values. The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver

changes to the new logic state. The new logic state is then maintained as long as the input stays

beyond the DC threshold. This approach is intended to provide predictable receiver timing in the

presence of input waveform ringing.

SW (Sampling

Window)

HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it

correctly. The setup and hold times determine the ideal strobe position in the sampling window.

Table 1–39. Glossary (Part 3 of 5)

Letter

Term

Definitions

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

Negative Channel (n) = V

Ground

0 V

- n

VIH(AC)

VIH(DC)

VREF

VIL(DC)

VIL(AC)

VOH

VOL

VCCIO

VSS

EP3C55 Datasheet(PDF) 29 Page - Altera Corporation

EP3C55 Datasheet(HTML) 29 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL