LM49150 datasheet(16/28 Pages) NSC

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Application Information

I2C COMPATIBLE INTERFACE

The LM49150 is controlled through an I2C compatible serial

interface that consists of a serial data line (SDA) and a serial

clock (SCL). The clock line is uni-directional. The data line is

bi-directional (open drain). The LM49150 and the master can

communicate at clock rates up to 400kHz. Figure 2 shows the

I2C interface timing diagram. Data on the SDA line must be

stable during the HIGH period of SCL. The LM49150 is a

transmit/receive slave-only device, reliant upon the master to

generate the SCL signal. Each transmission sequence is

framed by a START condition and a STOP condition (Figure

3). Each data word, device address and data, transmitted

over the bus is 8 bits long and is always followed by an ac-

knowledge pulse (Figure 4). The LM49150 device address is

11111000.

I2C INTERFACE POWER SUPPLY PIN (I2CV

DD)

The LM49150's I2C interface is powered up through the

I2CV

DD pin. The LM49150's I

2C interface operates at a volt-

age level set by the I2CV

DD pin which can be set independent

to that of the main power supply pin V

DD. This is ideal when-

ever logic levels for the I2C interface are dictated by a micro-

controller or microprocessor that is operating at a lower

supply voltage than the main battery of a portable system.

I2C BUS FORMAT

The I2C bus format is shown in Figure 4. The START signal,

the transition of SDA from HIGH to LOW while SCL is HIGH,

is generated, alerting all devices on the bus that a device ad-

dress is being written to the bus.

The 7-bit device address is written to the bus, most significant

bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the

master is writing to the slave device, R/W = 1 indicates the

master wants to read data from the slave device. Set R/W =

0; the LM49150 is a WRITE-ONLY device and will not re-

spond to the R/W = 1. The data is latched in on the rising edge

of the clock. Each address bit must be stable while SCL is

HIGH. After the last address bit is transmitted, the master de-

vice releases SDA, during which time, an acknowledge clock

pulse is generated by the slave device. If the LM49150 re-

ceives the correct address, the device pulls the SDA line low,

generating an acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit reg-

ister data word is sent. Each data bit should be stable while

SCL is HIGH. After the 8-bit register data word is sent, the

LM49150 sends another ACK bit. Following the acknowl-

edgement of the register data word, the master issues a

STOP bit, allowing SDA to go high while SCL is high.

300446s0

FIGURE 2. I2C Timing Diagram

300446s1

FIGURE 3. Start and Stop Diagram

LM49150 Datasheet(PDF) 16 Page - National Semiconductor (TI)

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